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Each array includes a plurality of words, wherein one word in each array indicates address words in the array having valid addresses.

At least one mask word provides mask information for at least one address word having a valid address, wherein the mask information for one address word indicates bits in the address word.

A network processor in routers implementing IPv4 and IPv6 tunneling maintains in memory lists of valid possible source addresses to use to validate the source address included with the IPv6 over IPv4 transmission.

validating addresses with google-65

Validating addresses with google

The network processor 50 further includes microengines 54 a, 54 b . The microengines may each comprise any programmable engine for processing packets. 72 n, if there is such a next array in the data structure 70. 76 l in the array 72 a, then the lower 12 bits of the validity/next block word 74 may comprise flags indicating whether each corresponding twelve address words include valid address data and the next 16 bits may be used as a next block index or pointer to a next array. In certain embodiments, the mask values within a mask word 78 a, 78 b, 78 c each comprise five bits indicating the bits in the 32-bit address word having valid address data. The described embodiments reduce processing overhead by minimizing the number of read operations that are performed to read in the valid source addresses to use during validation. Each array may include a plurality of words, where one word in each array indicates address words in the array having valid addresses, such as the next block/validity word 74. 76 l, having a valid address and the mask information for one address word may indicate bits in the address word comprising the address. The received address may be validated by performing operations 106 through 118. A determination is made (at block 108) from the word indicating valid addresses, e.g., the next block/valid word 74, those address words, e.g., 76 a . The received address is not validated if one matching address word is not located after processing all address words in a last array, e.g., 72 n, in the data structure 70. 76 l, matching the received address, which may be a source address in an IPv4 header 28 (), then the message encapsulated in the first network protocol is decapsulated (at block 116) to yield a message encapsulated in the second network protocol.

Microengine 54 c includes microblocks for processing IPv6 packets encapsulated within an IPv4 header 28 ( The network processor 50 further includes a Static Random Access Memory (SRAM) 58 to store information used during the processing of received packets, such as valid source addresses to check against the received source address in the IPv4 header 28 to validate that the source address of the device sending the packet is valid and authorized. Each array is comprised of a plurality of words, which may comprise 32 or any other number of bits. 76 n include valid addresses and a pointer to a next array, e.g., 72 b, 72 c . In one example, if there are twelve address words 76 a, 76 b . Following the validity/next block word 74 are five groups of 32-bit words, where each group includes a mask word 78 a, 78 b, and 78 c providing mask information for the address words 76 a, 76 b . A different number of mask bits may be used for a different number of bits in the address word. For instance, in one embodiment, each array, e.g., 72 a, comprises a 64 byte block that can be read from a single 16 32-bit SRAM register in a single SRAM read transaction. Further, at least one mask word, e.g., mask words 78 a, 78 b, 78 c, provides mask information for at least one address word, e.g., 76 a, 76 b . As discussed, in certain embodiments the data structure may be buffered in SRAM 58, which may be on or off board with respect to the network processor 50. 72 n, may indicate in one word a next linked array if there is a next linked array in the data structure. If (at block 112) the currently accessed array does include an address word, e.g., 76 a, 76 b . The source address is validated if there is a match.

Hosts using the Internet Protocol version 6 (IPv6) to communicate messages over a network can communicate over an Internet Protocol version 4 (IPv4) tunnel through a border router that encapsulates the IPv6 packets from the host within an IPv4 header as described in the publication “Transition Mechanisms for IPv6 Hosts and Routers”, Request for Comments (“RFC”) 2893 (Copyright 2000, The Internet Society).

The border routers that transmit the packets over the IPv4 tunnel implement both the IPv4 and IPv6 protocols.

A network processor, such as network processors 8 a, 8 b, comprises any device that executes programs to handle packets in a data network, such as processors on router line cards and network access equipment. Reading each array in a single memory transaction conserves read operations, which improves the speed of packet processing in network processing environments where a large volume of packets are being processed at very high speeds. 72 n, in the data structure, e.g., 70, is accessed. The received address is validated (at block 110) in response to determining that one address word in the array matches bits in the received address indicated in the mask information for the matching address word. 76 l may be performed by masking the received source address with the mask value indicated in the mask information for the address word being checked, which is in the mask word 78 a, 78 b, 78 c for the checked address word 76 a, 76 b . The next array is accessed to determine whether one address word in the next array matches bits in the received address indicated in the mask information for the matching address word.

illustrates one example of a network processor 50 that may (or may not) include a core processor 52 comprising a general purpose processor running an operating system, and may perform core device operations, including receiving, processing and transmitting packets. 54 n comprising high speed programmable processors specialized for packet processing. For example, mask word 78 a provides mask values for address words 76 a, 76 b, 76 c, 76 d; mask word 78 b provides mask values for address words 76 e, 76 f, 76 g, 76 h; and mask word 78 c provides mask values for address words 76 i, 76 j, 76 k, 76 l. 72 n is capable of being read in a single SRAM 58 read transaction. The data structure is processed (at block 104) to validate an address, such as a source address, received from a transmitting node, such as routers 6 a, 6 b (). When starting the process, the first array may 72 a is accessed. The operation of determining that the received source address matches one valid address word 76 a, 76 b . The next array to process may be determined from the next block pointer in the next block pointer/validity word 74.The transmitting router 6 a, 6 b encapsulates the IPv6 message received from the hosts 2 a, 2 b in an IPv4 header to transmit through an IPv4 tunnel 10 to the remote/receiving router 6 a, 6 b.The receiving router 6 a, 6 b decapsulates the IPv4 message to yield an IPv6 message to transmit to the local host 2 a, 2 b over the local IPv6 network 4 a, 4 b.The network processor 200 components may be implemented on a single integrated circuit die.An individual microengine 204 may offer multiple threads.Provided is an address validating data structure used for validating addresses.

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